FIG. 11 is a block diagram showing a typical liquid crystal display apparatus, having TFTs (Thin Film Transistors), of active matrix type. 3801 shows a TFT liquid crystal panel, 3802 shows a source driver IC (Integrated Circuit) having a plurality of source drivers, 3803 shows a gate driver IC having a plurality of gate drivers, 3804 shows a control circuit, and 3805 shows a liquid crystal driving power source (a power source circuit).
The control circuit 3804 sends a vertical synchronizing signal to the gate driver IC 3803, and sends a horizontal synchronizing signal to the source driver IC 3802 and the gate driver IC 3803, respectively. Display data (respective display data that are separated to R, G, and B) that have been externally applied are sent to the source driver IC 3802 in a form of digital signal via the control circuit 3804. In the source driver IC 3802, the display data that have been inputted are latched in a time sharing manner, and then, are subjected to digital to analog conversion in synchronization with the horizontal synchronizing signal outputted from the control circuit 3804 so as to output an analog voltage for the gradation display via a liquid crystal driving output terminal.
FIG. 12 is a structural diagram of the TFT liquid crystal panel. 3901 shows a pixel electrode, 3902 shows a pixel capacitance, 3903 shows a TFT switch (switching device), 3904 shows a source signal line, 3905 shows a gate signal line, and 3906 shows an opposite electrode.
To the source signal line 3904 a gradation display voltage that varies depending on the brightness of the display pixel is applied from the source driver IC 3802. To the gate signal lines 3905 scanning signals are applied from the gate driver IC 3803 so that the TFTs 3903 that are provided in a longitudinal direction are successively turned on. Voltages on the respective source signal lines 3904 are applied to the pixel electrodes 3901 that are connected with drains of the respective TFTs 3903 via the TFTs 3903 that are turned on. This causes the pixel capacitance 3902 formed between the pixel electrodes 3901 and the opposite electrode 3906 is charged, thereby resulting in that the light transmittance of the liquid crystal changes so as to carry out the display in accordance with the change in the light transmittance.
FIGS. 13 and 14 exemplify how the wave form of the liquid crystal driving voltage changes. 4001 and 4101 show wave forms of the driving voltages outputted from the source driver, respectively. 4002 and 4102 show wave forms of the driving voltages outputted from the gate driver, respectively. 4003 and 4103 show voltages (electric potentials) of the opposite electrodes. 4004 and 4104 show a voltage wave form of the pixel electrode.
The voltage (see the oblique lines in FIGS. 13 and 14) which is applied to the liquid crystal material is equal to the voltage difference between the pixel electrode 3901 and the opposite electrode 3906. It is necessary that the liquid crystal panel is driven by an alternating current voltage in order to secure the reliability for a long time. FIG. 13 shows the following case. More specifically, when the output voltage of the source driver is greater than the voltage of the opposite electrode 3906, the TFT 3903 is turned on in response to the output signal of the gate driver. A voltage showing a positive polarity with respect to the opposite electrode 3906 is applied to the pixel electrode 3901. Then, the TFT 3903 is turned off, so that such a voltage is maintained.
In contrast, FIG. 14 shows the following case. More specifically, when the output voltage of the source driver is smaller than the voltage of the opposite electrode 3906, the TFT 3903 is turned on in response to the output signal of the gate driver. A voltage showing a negative polarity with respect to the opposite electrode 3906 is applied to the pixel electrode 3901. Then, the TFT 3903 is turned off, so that such a voltage is maintained. Thus, when the wave form voltages of FIGS. 13 and 14 are alternately applied, it is possible that the liquid crystal material is driven by the applied voltage that is an alternating voltage.
FIG. 15 exemplifies the polarity arrangement, on the liquid crystal panel 3801, for the alternating of the driving voltage. This is called as a dot reverse driving. According to this type of driving, within a single display screen (frame), the positive polarity and negative polarity are alternated in a right and left direction and in an up and down direction, and the polarities are reversed for every frame. According to the driving, in the source driver IC 3802, when the voltage having a positive polarity is outputted via the odd-numbered output terminal for example, the voltage having a negative polarity is outputted via the even-numbered output terminal. In contrast, when the voltage having a negative polarity is outputted via the odd-numbered output terminal, the voltage having a positive polarity is outputted via the even-numbered output terminal.
FIG. 16 exemplifies a driving wave form of the source driver in the dot reverse driving. In FIG. 16, 4301 shows the output voltage wave form of the odd-numbered output terminal. 4302 shows the output voltage wave form of the even-numbered output terminal. 4303 shows the voltage of the opposite electrode 3906. As shown in FIG. 16, the voltages showing reverse polarities with respect to the opposite electrode 3906 are always outputted from the odd-numbered output terminal and the even-numbered output terminal, respectively.
FIG. 17 is one example of the block showing a structure of the source driver IC 3802. Here, the following description only deals with the associated source driver. Note that since a well known gate driver is adopted, the explanation thereof is omitted here. The respective display data (R, G, B) of the digital signal that has been inputted are stored in a sampling memory 4404 in response to a shift register 4403 in a time sharing manner, and then are transmitted to a hold memory 4405 in synchronization with the horizontal synchronizing signal in a lump. The shift register 4403 operates in response to a start pulse and a clock (CK). The data of the hold memory 4405 are sent via a level shifter circuit 4406 to a D/A (Digital to Analog) converter circuit 4407 so as to be converted into analog voltages, respectively. Such analog voltages are sent to an output circuit 4408 from which driving voltages for the gradation display (liquid crystal driving voltages) are outputted via respective liquid crystal output terminals. The respective display data are latched and maintained by the hold memory 4405 for a horizontal synchronizing period. Then, the display data are fetched and latched in synchronization with the next horizontal synchronizing signal.
FIGS. 18(a) and 18(b) are block diagrams exemplifying the output circuit of the source driver IC that carries out the dot reverse driving in accordance with a conventional art (the first conventional art) and showing the operation thereof. In FIGS. 18(a) and 18(b), only the blocks of the respective reference numerals 4405, 4407, and 4408 among the circuit elements shown in FIG. 17 are shown as circuits corresponding to two output terminals.
In FIGS. 18(a) and 18(b), 4501 shows a voltage follower which adopts operational amplifiers and is an output circuit that drives the odd-numbered output terminal. 4502 shows a voltage follower which adopts the same operational amplifiers as those of the voltage follower 4501 and is an output circuit that drives the even-numbered output terminal. Reference numerals 4503, 4504, 4505, and 4506 show switches for the output alternating that switches the polarity of the output voltage of the liquid crystal driving output, respectively. 4507 shows a D/A converter circuit in which a voltage having a positive polarity is subjected to the digital to analog conversion. 4508 shows a D/A converter circuit in which a voltage having a negative polarity is subjected to the digital to analog conversion. Reference numerals 4509 and 4510 show hold memories that hold the display data, respectively. 4511 shows the odd-numbered output terminal, and 4512 shows the even-numbered output terminal. In the operational amplifier 4501, a reference numeral 4513 is an operational amplifier of an N-channel MOS (Metal Oxide Semiconductor) input type. In the operational amplifier 4502, a reference numeral 4514 is an operational amplifier of an N-channel MOS input type. In the operational amplifier 4501, a reference numeral 4515 is an operational amplifier of a P-channel MOS input type. In the operational amplifier 4502, a reference numeral 4516 is an operational amplifier of a P-channel MOS input type.
The following description deals with how the circuit having the foregoing structure carries out the alternating of the wave form of the liquid crystal driving.
When the switches 4503 through 4506 for the output alternating are in the states shown in FIG. 18(a), the display data for the odd-numbered output terminal 4511 that have been stored in the hold memory 4509 are sent to the D/A converter circuit 4507 for the positive polarity, and are subjected to the digital to analog conversion so as to output an analog voltage to a liquid crystal panel 3801 from the odd-numbered output terminal 4511 via the voltage follower 4501. In this case, the output voltage becomes a liquid crystal driving voltage having a positive polarity.
In contrast, when the switches 4503 through 4506 for the output alternating are in the states shown in FIG. 18(b), the display data for the odd-numbered output terminal 4511 that have been stored in the hold memory 4509 are sent to the D/A converter circuit 4508 for the negative polarity, and are subjected to the digital to analog conversion so as to output an analog voltage to the liquid crystal panel from the odd-numbered output terminal 4511 via the voltage follower 4501. In this case, the output voltage becomes a liquid crystal driving voltage having a negative polarity.
The polarity of the driving voltage of the even-numbered output terminal 4512 is reversed to that of the odd-numbered output terminal 4511. Namely, when the switches 4503 through 4506 for the output alternating are in the states shown in FIG. 18(a), the display data for the even-numbered output terminal 4512 that have been stored in the hold memory 4510 are sent to the D/A converter circuit 4508 for the negative polarity, and are subjected to the digital to analog conversion so as to output an analog voltage to the liquid crystal panel from the even-numbered output terminal 4512 via the voltage follower 4502. In this case, the output voltage becomes a liquid crystal driving voltage having a negative polarity.
In contrast, when the switches 4503 through 4506 for the output alternating are in the states shown in FIG. 18(b), the display data for the even-numbered output terminal 4512 that have been stored in the hold memory 4510 are sent to the D/A converter circuit 4507 for the positive polarity, and are subjected to the digital to analog conversion so as to output an analog voltage to the liquid crystal panel from the even-numbered output terminal 4512 via the voltage follower 4502. In this case, the output voltage becomes a liquid crystal driving voltage having a positive polarity. In FIGS. 18(a) and 18(b), the signal flowing of the odd-numbered output terminal is shown among the foregoing operations. Thus, the states shown in FIGS. 18(a) and 18(b) are alternately switched by the switches 4503 through 4506 for the output alternating in accordance with the frame reversion, thereby carrying out the alternating of the driving wave form required for driving the liquid crystal panel 3801.
According to the circuit configuration shown in FIGS. 18(a) and 18(b), a single output terminal is always driven by the same operational amplifiers both for the case of the output of the voltage having a positive polarity and the output of the voltage having a negative polarity. In general, as one of the important functions of the output terminal of the liquid crystal driving circuit, the output dynamic range having a full range of the operating power source voltages is required. When it is assumed to use MOS transistors of enhance type that are used in a general LSI, in order not to have areas in which the MOS transistors do not appropriately operate with their threshold voltages, as shown in FIGS. 18(a) and 18(b), it is necessary that a single voltage follower circuit 4501 has both the operational amplifier 4513 of N-channel MOS transistor input type and the operational amplifier 4515 of P-channel MOS transistor input type. This causes the scale of the circuit to become large so as to result in the increase of the chip size in the case where the output circuit is subjected to the LSI. Furthermore, the power consumption of the circuit becomes large because two operational amplifier circuits are provided per one output.
FIGS. 19(a) and 19(b) are block diagrams exemplifying the output circuit of the source driver IC that carries out the dot reverse driving in accordance with another conventional art (the second conventional art) and showing the operation thereof. In FIGS. 19(a) and 19(b), only the blocks of the respective reference numerals 4405, 4407, and 4408 among the circuit elements (the respective blocks) shown in FIG. 17 are shown as circuits corresponding to two output terminals.
In FIGS. 19(a) and 19(b), 4601 shows a voltage follower using an operational amplifier of N-channel MOS transistor input type. 4602 shows a voltage follower using an operational amplifier of P-channel MOS transistor input type. Reference numerals 4603, 4604, 4605, and 4606 show switches for switching the polarity of the liquid crystal driving output voltage. 4607 shows a D/A converter circuit in which a voltage having a positive polarity is subjected to the digital to analog conversion. 4608 shows a D/A converter circuit in which a voltage having a negative polarity is subjected to the digital to analog conversion. Reference numerals 4609 and 4610 show hold memories that hold the display data, respectively. 4611 shows the odd-numbered output terminal, and 4612 shows the even-numbered output terminal.
The alternating of the output voltage shown in FIGS. 19(a) and 19(b), like the case shown in FIGS. 18(a) and 18 (b), is carried out by the switches 4603 through 4606 for the output alternating. The difference therebetween resides in the following points (a) through (c). Namely, (a) the output signal of the D/A converter circuit 4607 for the positive polarity is directly sent to the operational amplifier 4601 of N-channel MOS transistor input type, (b) the output signal of the D/A converter circuit 4608 for the negative polarity is directly sent to the operational amplifier 4602 of P-channel MOS transistor input type, and (c) the output signals of the respective operational amplifiers are sent to target output terminals via the switches 4603 and 4604.
Note that it is necessary to only provide a circuit of N-channel input type as the operational amplifier because the D/A converter circuit 4607 for the positive polarity outputs a signal having a voltage of not less than the half of the operating power source voltage. Similarly, it is necessary to only provide a circuit of P-channel input type as the operational amplifier because the D/A converter circuit 4608 for the positive polarity outputs a signal having a voltage of not more than the half of the operating power source voltage. According to the structure shown in FIGS. 19 (a) and 19(b), the number of the operational amplifiers for each output terminal is reduced to half of the structure shown in FIGS. 18(a) and 18(b). This allows to reduce the size of a chip and ensure the low power consumption.
However, according to the structure shown in FIGS. 19(a) and 19(b), different operational amplifiers that drive a single output are used depending on whether it is of positive polarity type or of negative polarity type. More specifically, the output terminal for the liquid crystal driving shown in FIGS. 19(a) and 19(b) is driven by the operational amplifier 4601 when a voltage having positive polarity should be outputted (see FIG. 19(a)), while the output terminal is driven by the operational amplifier 4602 when a voltage having negative polarity should be outputted (see FIG. 19(b)). The following description deals with a case where the operational amplifiers 4601 and 4602 have offset voltages that happen to be generated due to the reason such as the unevenness of the characteristics occurred by the manufacturing process, respectively.
FIG. 20 shows wave forms of the liquid crystal voltage in the case where the operational amplifier 4601 has an offset voltage A that happens to be generated and the operational amplifier 4602 has an offset voltage B that happens to be generated. As shown in FIG. 20, the deviations from respective expectation voltages vary depending on whether a voltage having positive or negative polarity should be outputted. Accordingly, the average voltage of the driving voltages that are applied to the liquid crystal display pixel contains a component of (A-B) indicative of the difference between the two deviations as an error voltage. The error voltage happens to be generated for every driving output terminals. This allows the difference in the voltages applied to the respective pixels in the liquid crystal display apparatus to occur and causes the unevenness of display.
For comparison, FIG. 21 shows the wave form of the liquid crystal driving voltage for the structure shown in FIGS. 18(a) and 18(b). According to the structure shown in FIGS. 18(a) and 18(b), a single output circuit drives the voltages having positive and negative polarities, respectively. This results in that the deviations from the respective expectation voltages are always equal to each other. The deviations are functioned to be canceled between the voltages having positive and negative polarities which are applied to the pixel. According to the structure shown in FIGS. 18(a) and 18(b), the unevenness of the deviations among the output terminals for the liquid crystal driving is averaged in the display pixel. Thus, no problem arises during the display.
The foregoing second conventional art (see FIG. 19) deals with the case where the voltages having positive and negative polarities should be outputted by the separate operational amplifier circuits, respectively. In contrast, well known is the third conventional art (for example, see Japanese unexamined patent publication No. 11-305735 (publication date: Nov. 5, 1999) in which the respective further reductions of the circuit scale and the power consumption are realized. The following description deals with the third conventional art with reference to FIG. 22.
FIG. 22 exemplifies the structure of a differential amplifier circuit in accordance with the third conventional art. Note that FIG. 22 shows the case where N-channel MOS transistors are used as the inputting transistors.
In FIG. 22, the reference numerals 101 and 102 indicate the input transistors of N-channel MOS type, respectively. The reference numeral 103 indicates a constant current source that supplies the differential amplifier circuit with the operational current. The reference numeral 104 indicates a load resistor (resistor element) of the input transistor 101. The reference numeral 105 indicates a load resistor (resistor element) of the input transistor 102. The reference numerals 106 and 107 indicate switches for respectively switching the input signal. The reference numerals 108 and 109 indicate switches for respectively switching the output signal. The reference numeral 110 indicates a noninverted input terminal (common-mode input terminal). The reference numeral 111 indicates an inverted input terminal (reverse-phase input terminal). The reference numeral 112 indicates a noninverted output terminal. The reference numeral 113 indicates an inverted output terminal. The reference numeral 114 indicates a changeover signal input terminal via which a signal for simultaneously switching the switches 106 through 109 is inputted.
A differential amplifier circuit is composed of the input transistor 101, the load resistor 104, the input transistor 102, and the load resistor 105. The input transistors 101 and 102 constitute a differential pair. The switches 106 through 109 are controlled by the changeover signal 114 in an interlocking manner.
FIG. 23 shows one example of operation of the circuit shown in FIG. 22. FIG. 24 shows another example of operation of the circuit shown in FIG. 22. The following description deals with the operation of the differential amplifier circuit with reference to FIGS. 23 and 24.
According to the operation shown in FIG. 23, the noninverted input terminal 110 is connected with the gate of the input transistor 101 via the switch 106. An input signal inputted via the noninverted input terminal 110 is outputted by the function of the load resistor 104, that is connected with the drain of the input transistor 101, from an inverted output terminal 113 as an inverted output signal via the switch 109. The inverted input terminal 111 is connected with the gate of the input transistor 102 via the switch 107. An input signal inputted via the inverted input terminal 111 is outputted by the function of the load resistor 105, that is connected with the drain of the input transistor 102, from a noninverted output terminal 112 as a noninverted output signal via the switch 108. Namely, the noninverted input signal is amplified by the input transistor 101 and the load resistor 104, while the inverted input signal is amplified by the input transistor 102 and the load resistor 105.
In contrast, according to the operation shown in FIG. 24, the noninverted input terminal 110 is connected with the gate of the input transistor 102 via the switch 107. An input signal inputted via the noninverted input terminal 110 is outputted by the function of the load resistor 105, that is connected with the drain of the input transistor 102, from the inverted output terminal 113 as an inverted output signal via the switch 109. The inverted input terminal 111 is connected with the gate of the input transistor 101 via the switch 106. An input signal inputted via the inverted input terminal 111 is outputted by the function of the load resistor 104, that is connected with the drain of the input transistor 101, from the noninverted output terminal 112 as a noninverted output signal via the switch 108. Namely, the noninverted input signal is amplified by the input transistor 102 and the load resistor 105, while the inverted input signal is amplified by the input transistor 101 and the load resistor 104.
As mentioned above, the amplifier circuits for the noninverted input signal and for the inverted input signal are entirely changed and used according to the operations shown in FIGS. 23 and 24.
With reference to FIGS. 25 and 26, the following description deals with the case where there exists the discrepancy of the characteristics, that happens to occur due to the reason of the manufacturing process or other reasons, between the input transistors 101 and 102 and/or the load resistors 104 and 105 that constitute the differential amplifier circuit.
When the difference occurs between the two circuit elements that should have originally the same characteristic, each output voltage deviates from its ideal voltage, so that an offset voltage occurs. Such deviations can be explained by a model in which one of the input terminals is connected with a constant voltage source. FIGS. 25 and 26 show an example. The reference numeral 115 shown in FIGS. 25 and 26 is the model of the offset voltage that is realized by a single constant voltage source. Note that the switching device shown in FIG. 25 is in the same conditions as those shown in FIG. 23, and that the switching device shown in FIG. 26 is in the same conditions as those shown in FIG. 24.
In FIG. 25, the constant voltage source 115 is connected with the inverted input terminal 111 via the switch 107. In FIG. 26, the constant voltage source 115 is connected with the noninverted input terminal 110 via the switch 107. Thus, the differential amplifier circuit uses the switches 106 through 109. This allows the circuit to switch between (a) the condition in which an offset that happens to occur due to the unevenness in the differential amplifier circuit is inputted to the inverted input terminal 111 and (b) the condition in which such an offset is inputted to the noninverted input terminal 110. According to such two kinds of conditions, the offsets of the noninverted output terminal 110 and the inverted output terminal 111 have a same absolute value and have polarities that are reversed to each other.
Thus, in the case where the operational amplifier has an offset voltage that happens to be generated due to the reasons such as the characteristic unevenness occurred by the manufacturing process, (a) the deviation from the expectation voltage when the offset voltage having positive polarity should be outputted and (b) the deviation from the expectation voltage when the offset voltage having negative polarity should be outputted are equal to each other. Accordingly, when the above operational amplifier is used in a liquid crystal driving circuit, there occurs no difference in the voltages that are applied to the respective pixels of the liquid crystal display apparatus. Thus, it is ensured to avoid the display unevenness.
FIG. 27 shows another example of the differential amplifier circuit in accordance with the second conventional art. FIG. 27 shows the case in which P-channel MOS transistors are used as the input transistors.
In FIG. 27, the reference numerals 601 and 602 indicate the input transistors of P-channel MOS type, respectively. The reference numeral 603 indicates a constant current source that supplies the differential amplifier circuit with the operational current. The reference numeral 604 indicates a load resistor (resistor element) of the input transistor 601. The reference numeral 605 indicates a load resistor (resistor element) of the input transistor 602. The reference numerals 606 and 607 indicate switches for respectively switching the input signals. The reference numerals 608 and 609 indicate switches for respectively switching the output signals. The reference numeral 610 indicates a noninverted input terminal (common-mode input terminal). The reference numeral 611 indicates an inverted input terminal (reverse-phase input terminal). The reference numeral 612 indicates a noninverted output terminal. The reference numeral 613 indicates an inverted output terminal. The reference numeral 614 indicates a changeover signal input terminal via which a signal for simultaneously switching the switches 606 through 609 is inputted.
The following description deals with the operation of FIG. 27 with reference to FIGS. 28 and 29.
According to the operation shown in FIG. 28, the noninverted input terminal 610 is connected with the gate of the input transistor 601 via the switch 606. An input signal inputted via the noninverted input terminal 610 is outputted by the function of the load resistor 604, that is connected with the drain of the input transistor 601, from an inverted output terminal 613 as an inverted output signal via the switch 609. The inverted input terminal 611 is connected with the gate of the input transistor 602 via the switch 607. An input signal inputted via the inverted input terminal 611 is outputted by the function of the load resistor 605, that is connected with the drain of the input transistor 602, from a noninverted output terminal 612 as a noninverted output signal via the switch 608. Namely, the noninverted input signal is amplified by the input transistor 601 and the load resistor 604, while the inverted input signal is amplified by the input transistor 602 and the load resistor 605.
In contrast, according to the operation shown in FIG. 29, the noninverted input terminal 610 is connected with the gate of the input transistor 602 via the switch 607. An input signal inputted via the noninverted input terminal 610 is outputted by the function of the load resistor 605, that is connected with the drain of the input transistor 602, from the inverted output terminal 613 as an inverted output signal via the switch 609. The inverted input terminal 611 is connected with the gate of the input transistor 601 via the switch 606. An input signal inputted via the inverted input terminal 611 is outputted by the function of the load resistor 604, that is connected with the drain of the input transistor 601, from the noninverted output terminal 612 as a noninverted output signal via the switch 608. Namely, the noninverted input signal is amplified by the input transistor 602 and the load resistor 605, while the inverted input signal is amplified by the input transistor 601 and the load resistor 604.
As mentioned above, the amplifier circuits for the noninverted input signal and for the inverted input signal are entirely changed and used according to the operations shown in FIGS. 28 and 29.
With reference to FIGS. 30 and 31, the following description deals with the case where there exists the discrepancy of the characteristics, that happens to occur due to the reason of the manufacturing process or other reasons, between the input transistors 601 and 602 and/or the load resistors 604 and 605 that constitute the differential amplifier circuit.
When the difference occurs between the two circuit elements that should have originally the same characteristic, each output voltage deviates from its ideal voltage, so that an offset voltage occurs. Such deviations can be explained by a model in which one of the input terminals is connected with a constant voltage source. FIGS. 30 and 31 show an example. The reference numeral 615 shown in FIGS. 30 and 31 is the model of the offset voltage that is realized by a single constant voltage source. Note that the switching device shown in FIG. 30 is in the same conditions as those shown in FIG. 28, and that the switching device shown in FIG. 31 is in the same conditions as those shown in FIG. 29.
In FIG. 30, the constant voltage source 615 is connected with the inverted input terminal 611 via the switch 607. In FIG. 31, the constant voltage source 615 is connected with the noninverted input terminal 610 via the switch 607. Thus, the differential amplifier circuit uses the switches 606 through 609. This allows the circuit to switch between (a) the condition in which an offset that happens to occur due to the unevenness in the differential amplifier circuit is inputted to the inverted input terminal 611 and (b) the condition in which such an offset is inputted to the noninverted input terminal. According to such two kinds of conditions, the offsets of the noninverted output terminal 610 and the inverted output terminal 611 have a same absolute value and have polarities that are reversed to each other.
Thus, in the case where the operational amplifier has an offset voltage that happens to be generated due to the reasons such as the characteristic unevenness occurred by the manufacturing process, (a) the deviation from the expectation voltage when the offset voltage having positive polarity should be outputted and (b) the deviation from the expectation voltage when the offset voltage having negative polarity should be outputted are equal to each other. Accordingly, when the above operational amplifier is used in a liquid crystal driving circuit, there occurs no difference in the voltages that are applied to the respective pixels of the liquid crystal display apparatus. Thus, it is ensured to avoid the display unevenness.
FIG. 32 shows a circuit configuration in which the load element of the differential amplifier circuit shown in FIG. 22 is replaced with an active load having a current mirror structure. FIG. 32 shows the case where N-channel MOS transistors are used as the input transistors.
In FIG. 32, the reference numerals 1101 and 1102 indicate the input transistors of N-channel MOS type, respectively. The reference numeral 1103 indicates a constant current source that supplies the differential amplifier circuit with the operational current. The reference numeral 1104 indicates a load transistor, made of P-channel MOS, of the input transistor 1101. The reference numeral 1105 indicates a load transistor, made of P-channel MOS, of the input transistor 1102. The reference numerals 1106 and 1107 indicate switches for respectively switching the input signals. The reference numerals 1108 and 1109 indicate switches for respectively switching the output signals. The reference numeral 1110 indicates a noninverted input terminal (common-mode input terminal). The reference numeral 1111 indicates an inverted input terminal (reverse-phase input terminal). The reference numeral 1112 indicates a noninverted output terminal. The reference numeral 1113 indicates an inverted output terminal. The reference numeral 1114 indicates a changeover signal input terminal via which a signal for simultaneously switching the switches 1106 through 1109 is inputted.
The differential amplifier circuit is different from the structure (passive load) shown in FIG. 22 in that the load element is an active load having such a current mirror structure made of transistors. In the operation corresponding to the operation shown in FIG. 23, a noninverted input signal is amplified by the input transistor 1101 and the load transistor 1104, while an inverted input signal is amplified by the input transistor 1102 and the load transistor 1105. In contrast, in the operation corresponding to the operation shown in FIG. 24, a noninverted input signal is amplified by the input transistor 1102 and the load transistor 1105, while an inverted input signal is amplified by the input transistor 1101 and the load transistor 1104.
According to any one of the foregoing cases, the load transistors 1104 and 1105 constitute a current mirror structure. This allows that the current flowing through the load transistors 1104 and 1105 are always equal to each other even when the characteristic unevenness occurs between the two load transistors 1104 and 1105. This results in that the noninverted input signal and the inverted input signal are amplified in accordance with the same amplification, thereby ensuring to obtain an output wave form that is bisymmetry.
As mentioned above, the amplifier circuits for the noninverted input signal and for the inverted input signal are entirely changed and used even in the case of the structure shown in FIG. 32.
Even in the case where there exists the discrepancy of the characteristics, that happens to occur due to the reason of the manufacturing process or other reasons, between the input transistors 1101 and 1102 that constitute the differential amplifier circuit, the structure similar to that shown in FIG. 22 is realized although the detail is not described here. Thus, the differential amplifier circuit uses the switches 1106 through 1109. This allows the circuit to switch between (a) the condition in which an offset that happens to occur due to the unevenness in the differential amplifier circuit is inputted to the inverted input terminal 1111 and (b) the condition in which such an offset is inputted to the noninverted input terminal 1110. According to such two kinds of conditions, the offsets of the noninverted output terminal 1110 and the inverted output terminal 1111 have a same absolute value and have polarities that are reversed to each other.
Thus, in the case where the operational amplifier has an offset voltage that happens to be generated due to the reasons such as the characteristic unevenness occurred by the manufacturing process, (a) the deviation from the expectation voltage when the offset voltage having positive polarity should be outputted and (b) the deviation from the expectation voltage when the offset voltage having negative polarity should be outputted are equal to each other. This results in that the difference component between the two deviations is not remained as an error voltage in the average voltage of the driving voltages that are applied to the liquid crystal display pixels. Accordingly, when the above operational amplifier is used in a liquid crystal driving circuit, there occurs no difference in the voltages that are applied to the respective pixels of the liquid crystal display apparatus. Thus, it is ensured to avoid the display unevenness.
FIG. 33 shows a circuit configuration in which the load element of the differential amplifier circuit shown in FIG. 27 is replaced with an active load having a current mirror structure. FIG. 33 shows the case in which P-channel MOS transistors are used as the input transistors.
In FIG. 33, the reference numerals 1201 and 1202 indicate the input transistors of P-channel MOS type, respectively. The reference numeral 1203 indicates a constant current source that supplies the differential amplifier circuit with the operational current. The reference numeral 1204 indicates a load transistor (resistor element) of the input transistor 1201. The reference numeral 1205 indicates a load transistor (resistor element) of the input transistor 1202. The reference numerals 1206 and 1207 indicate switches for respectively switching the input signals. The reference numerals 1208 and 1209 indicate switches for respectively switching the output signals. The reference numeral 1210 indicates a noninverted input terminal (common-mode input terminal). The reference numeral 1211 indicates an inverted input terminal (reverse-phase input terminal). The reference numeral 1212 indicates a noninverted output terminal. The reference numeral 1213 indicates an inverted output terminal. The reference numeral 1214 indicates a changeover signal input terminal via which a signal for simultaneously switching the switches 1206 through 1209 is inputted.
The circuit configuration shown in FIG. 33 is different from the structure (passive load) shown in FIG. 27 in that the load element is an active load having such a current mirror structure made of transistors. In the operation corresponding to the operation shown in FIG. 28, a noninverted input signal is amplified by the input transistor 1201 and the load transistor 1204, while an inverted input signal is amplified by the input transistor 1202 and the load transistor 1205. In contrast, in the operation corresponding to the operation shown in FIG. 29, a noninverted input signal is amplified by the input transistor 1202 and the load transistor 1205, while an inverted input signal is amplified by the input transistor 1201 and the load transistor 1204.
According to any one of the foregoing cases, the load transistors 1204 and 1205 constitute a current mirror structure. This allows that the current flowing through the load transistors 1204 and 1205 are always equal to each other even when the characteristic unevenness occurs between the two load transistors 1204 and 1205. This results in that the noninverted input signal and the inverted input signal are amplified in accordance with the same amplification, thereby ensuring to obtain an output wave form that is bisymmetry.
As mentioned above, the amplifier circuits for the noninverted input signal and for the inverted input signal are entirely changed and used even in the case of the structure shown in FIG. 33.
Even in the case where there exists the discrepancy of the characteristics, that happens to occur due to the reason of the manufacturing process or other reasons, between the input transistors 1201 and 1202 that constitute the differential amplifier circuit, the structure similar to that shown in FIG. 27 is realized although the detail is not described here. Thus, the differential amplifier circuit uses the switches 1206 through 1209. This allows to switch between (a) the condition in which an offset that happens to occur due to the unevenness in the differential amplifier circuit is inputted to the inverted input terminal 1211 and (b) the condition in which such an offset is inputted to the noninverted input terminal 1210. According to such two kinds of conditions, the offsets of the noninverted output terminal 1210 and the inverted output terminal 1211 have a same absolute value and have polarities that are reversed to each other.
Thus, in the case where the operational amplifier has an offset voltage that happens to be generated due to the reasons such as the characteristic unevenness occurred by the manufacturing process, (a) the deviation from the expectation voltage when the offset voltage having positive polarity should be outputted and (b) the deviation from the expectation voltage when the offset voltage having negative polarity should be outputted are equal to each other. This results in that the difference component between the two deviations is not remained as an error voltage in the average voltage of the driving voltages that are applied to the liquid crystal display pixels. Accordingly, when the above operational amplifier is used in a liquid crystal driving circuit, there occurs no difference of the voltages that are applied to the respective pixels of the liquid crystal display apparatus. Thus, it is ensured to avoid the display unevenness.
The following description deals with an example which embodies a differential amplifier circuit 1301 that is equivalent to the differential amplifier circuit shown in FIG. 32, switches, and an output section with reference to FIG. 34. Note that each of the operational amplifiers shown in FIG. 34 is of N-channel MOS input type.
In FIG. 34, the reference numeral 1301 indicates the differential amplifier circuit shown in FIG. 32, the reference numeral 1302 indicates a noninverted input terminal, the reference numeral 1303 indicates an inverted input terminal. The reference numerals 1304 and 1305 indicate switch changeover signal input terminals, respectively. The reference numerals 1306 through 1309 indicate switches, respectively. The reference numerals 1310 through 1313 indicate switches, respectively. The reference numerals 1314 and 1315 are input transistors of N-channel MOS type, respectively. The reference numerals 1316 and 1317 indicate load transistors of P-channel MOS type that are active loads for the input transistors, respectively. The reference numeral 1318 indicates an output transistor of P-channel MOS type. The reference numeral 1319 indicates an output transistor of N-channel MOS type. The reference numeral 1320 indicates an output terminal. The reference numeral 1321 indicates a bias voltage input terminal for providing an operating point of the operational amplifier. A circuit in which the differential amplifier circuit 1301 is replaced with the load resistor shown in FIG. 22 carries out the same operations as the following description. Therefore, the detail explanation is omitted here.
In FIG. 34, the reference numerals 1304 and 1305 correspond to the switch changeover signal input terminal 1114 shown in FIG. 32. The terminals 1304 and 1305 receive respective signals whose polarities are reversed to each other. The following description deals with the circuit operation in accordance with the switch changeover signal with reference to FIGS. 35 and 36.
In FIG. 34, the input transistors 1314 and 1315 correspond to the input transistors 1101 and 1102 shown in FIG. 32, respectively. The load transistors 1316 and 1317 correspond to the load transistors 1104 and 1105 shown in FIG. 32, respectively.
In FIG. 34, the reference numerals 1307 and 1309 correspond to the switch 1106 shown in FIG. 32, the reference numerals 1306 and 1308 correspond to the switch 1107 shown in FIG. 32, the reference numerals 1310 and 1313 correspond to the switch 1108 shown in FIG. 32, the reference numerals 1311 and 1312 correspond to the switch 1109 shown in FIG. 32, and a transistor 1322 corresponds to the constant current source 1103 shown in FIG. 32.
When a signal of “L” level (low level) is applied to the switch changeover signal input terminal 1304, the switches 1306, 1307, 1310, and 1311 are turned on, because the switches are P-channel MOS transistors as shown in FIG. 35. In this case, since a signal of “H” level (high level) is applied to the switch changeover signal input terminal 1305, the switches 1308, 1309, 1312, and 1313 are turned off. A noninverted input signal 1302 is sent to the input transistor 1315 via the switch 1306. An inverted input signal 1303 is sent to the input transistor 1314 via the switch 1307. A gate signal is sent to the load transistors 1316 and 1317 via the switch 1310. A gate signal is sent to the output transistor 1318 via the switch 1311. In the case of FIG. 35, the noninverted input signal is amplified by the circuit that is constituted by the input transistor 1315 and the load transistor 1317, while the inverted input signal is amplified by the circuit that is constituted by the input transistor 1314 and the load transistor 1316.
When a signal of “L” level is applied to the switch changeover signal input terminal 1305, the switches 1308, 1309, 1312, and 1313 are turned on, in FIG. 36. In this case, since a signal of “H” level is applied to the switch changeover signal input terminal 1304, the switches 1306, 1307, 1310, and 1311 are turned off. The noninverted input signal at terminal 1302 is sent to the input transistor 1314 via the switch 1308. The inverted input signal at terminal 1303 is sent to the input transistor 1315 via the switch 1309. The gate signal is sent to the load transistors 1316 and 1317 via the switch 1313. The gate signal is sent to the output transistor 1318 via the switch 1312. In the case of FIG. 36, the noninverted input signal is amplified by the circuit that is constituted by the input transistor 1314 and the load transistor 1316, while the inverted input signal is amplified by the circuit that is constituted by the input transistor 1315 and the load transistor 1317.
As shown in FIGS. 35 and 36, the present differential amplifier circuit switches the switches 1306 through 1313 so that the amplifier circuits for the noninverted input signal and for the inverted input signal can be replaced with each other. This allows that even when offsets that happen to occur due to the unevenness in the manufacturing process of the differential amplifier circuit is generated, the offsets have a same absolute value and have polarities that are reversed to each other for the foregoing two conditions. Accordingly, it can be realized by changing the switches 1306 through 1313 that the offsets, having the unevenness, occurred in the operational amplifier have a same absolute value and have polarities that are reversed to each other. This allows to cancel the offsets.
The following description deals with an example which embodies a differential amplifier circuit 1601 that is equivalent to the differential amplifier circuit shown in FIG. 33, switches, and an output section with reference to FIG. 37. Note that FIG. 37 shows an operational amplifier of P-channel MOS input type.
In FIG. 37, the reference numeral 1602 indicates a noninverted input terminal. The reference numeral 1603 indicates an inverted input terminal. The reference numerals 1604 and 1605 indicate switch changeover signal input terminals, respectively. The reference numerals 1606 through 1609 indicate switches, respectively. The reference numerals 1610 through 1613 indicate switches, respectively. The reference numerals 1614 and 1615 are input transistors of P-channel MOS type, respectively. The reference numerals 1616 and 1617 indicate load transistors of N-channel MOS type that are active loads for the input transistors, respectively. The reference numeral 1618 indicates an output transistor of N-channel MOS type. The reference numeral 1619 indicates an output transistor of P-channel MOS type. The reference numeral 1620 indicates an output terminal. The reference numeral 1621 indicates a bias voltage input terminal for providing an operating point of the operational amplifier. A circuit in which the differential amplifier circuit 1601 is replaced with the load resistor shown in FIG. 27 carries out the same operations as follows. Therefore, the detail explanation is omitted here.
In FIG. 37, the input transistors 1614 and 1615 correspond to the input transistors 1201 and 1202 shown in FIG. 33, respectively. The load transistors 1616 and 1617 correspond to the load transistors 1204 and 1205 shown in FIG. 33, respectively. In FIG. 37, the reference numerals 1607 and 1609 correspond to the switch 1206 shown in FIG. 33, the reference numerals 1606 and 1608 correspond to the switch 1207 shown in FIG. 33, the reference numerals 1611 and 1612 correspond to the switch 1209 shown in FIG. 33, and the reference numeral 1622 corresponds to the constant current source 1203 in FIG. 33.
When a signal of “H” level (high level) is applied to the switch changeover signal input terminal 1604, the switches 1606, 1607, 1610, and 1611 are turned on, because the switches are N-channel MOS type transistors as shown in FIG. 38. In this case, since a signal of “L” level (low level) is applied to the switch changeover signal input terminal 1605, the, switches 1608, 1609, 1612, and 1613 are turned off. A noninverted input signal at terminal 1602 is sent to the input transistor 1615 via the switch 1606. An inverted input signal at terminal 1603 is sent to the input transistor 1614 via the switch 1607. A gate signal is sent to the load transistors 1616 and 1617 via the switch 1610. A gate signal is sent to the output transistor 1618 via the switch 1611. In the case of FIG. 38, the noninverted input signal is amplified by the circuit that is constituted by the input transistor 1615 and the load transistor 1617, while the inverted input signal is amplified by the circuit that is constituted by the input transistor 1614 and the load transistor 1616.
When a signal of “H” level (high level) is applied to the switch changeover signal input terminal 1605, the switches 1608, 1609, 1612, and 1613 are turned on, in FIG. 39. In this case, since a signal of “L” level is applied to the switch changeover signal input terminal 1604, the switches 1606, 1607, 1610, and 1611 are turned off. The noninverted input signal at terminal 1602 is sent to the input transistor 1614 via the switch 1608. The inverted input signal at terminal 1603 is sent to the input transistor 1615 via the switch 1609. The gate signal is sent to the load transistors 1616 and 1617 via the switch 1613. The gate signal is sent to the output transistor 1618 via the switch 1612. In the case of FIG. 39, the noninverted input signal is amplified by the circuit that is constituted by the input transistor 1614 and the load transistor 1616, while the inverted input signal is amplified by the circuit that is constituted by the input transistor 1615 and the load transistor 1617.
As shown in FIGS. 38 and 39, the present differential amplifier circuit switches the respective switches 1606 through 1613 so that the amplifier circuits for the noninverted input signal and for the inverted input signal can be replaced with each other. This allows that even when offsets that happen to occur due to the unevenness in the manufacturing process of the differential amplifier circuit is generated, the offsets have a same absolute value and have polarities that are reversed to each other for the foregoing two conditions. Accordingly, it can be realized by changing the switches 1606 through 1613 that the offsets, having the unevenness, occurred in the operational amplifier have a same absolute value and have polarities that are reversed to each other. Note that a dotted line indicates the flow of the signals in FIGS. 38 and 39.
FIGS. 40 and 41 are block diagrams showing a liquid crystal driving circuit that adopts the foregoing differential amplifier circuit and carries out the dot reverse driving. FIGS. 40 and 41 respectively show only the part of two neighboring output circuits, and show the respective operations for the case where the polarity of the liquid crystal driving voltage is changed.
In FIGS. 40 and 41, the reference numeral 2101 indicates the operational amplifier of N-channel MOS transistor input type shown in FIG. 34, the reference numeral 2102 indicates the operational amplifier of P-channel MOS transistor input type shown in FIG. 37. The reference numeral 2103 indicates a D/A converter circuit that generates a liquid crystal driving voltage having a positive polarity. The reference numeral 2104 indicates a D/A converter circuit that generates a liquid crystal driving voltage having a negative polarity. The reference numerals 2105 through 2108 indicate switches by which the liquid crystal driving voltage is made to be an A.C. voltage. The reference numeral 2109 indicates a latch circuit that stores the display data of the odd-numbered output terminals, and the reference numeral 2110 indicates a latch circuit that stores the display data of the even-numbered output terminals. The reference numeral 2111 indicates the odd-numbered output terminal, and the reference numeral 2112 indicates the even-numbered output terminal. The reference numeral 2113 indicates an alternation switch changeover signal input, and the reference numeral 2114 indicates the switch changeover signal for the operational amplifier shown in FIGS. 34 and 37. Note that the latch circuits 2109 and 2110 indicate the hold memory shown in FIG. 17 and the explanation is made without a level shifter circuit (with omitting a level shifter circuit).
The following description deals with the operation of the odd-numbered output terminal with reference to these drawings. As to the even-numbered output terminal, the same operation is carried out except for the fact that the polarity of the driving voltage is reversed to that of the odd-numbered output terminal. Therefore, the detail explanation is omitted here.
FIG. 40 shows the case where (a) a driving voltage having positive polarity is outputted via the odd-numbered output terminal 2111 and (b) a driving voltage having negative polarity via the even-numbered output terminal 2112. In this case, the display data of the odd-numbered output terminal is sent from the latch circuit 2109 to the positive-polarity D/A converter circuit 2103 via the switch 2105. The output signal of the positive-polarity D/A converter circuit 2103 is sent to the operational amplifier 2101 so as to be outputted from the odd-numbered output terminal 2111 via the switch 2107 (see the thick line shown in FIG. 40).
FIG. 41 shows the case where (a) a driving voltage having negative polarity is outputted via the odd-numbered output terminal 2111 and (b) a driving voltage having positive polarity via the even-numbered output terminal 2112. In this case, the display data of the even-numbered output terminal is sent from the latch circuit 2109 to the negative-polarity D/A converter circuit 2104 via the switch 2106. The output signal of the negative-polarity D/A converter circuit 2104 is sent to the operational amplifier 2102 so as to be outputted from the odd-numbered output terminal 2111 via the switch 2107 (see the thick line shown in FIG. 41).
The following description deals with the case where each operational amplifier has an offset voltage that happens to be generated by the characteristic unevenness due to the reason occurred in the manufacturing process of the operational amplifier or other reasons. As has been described, the switch changeover signal allows the polarity of the offset voltage in the operational amplifier to be reversed. In this case, since the absolute values of the offset voltages are equal to each other, it is assumed that (a) the changing into an offset voltage A or an offset voltage −A is made by the operational amplifier 2101 and (b) the changing into an offset voltage B or an offset voltage −B is made by the operational amplifier 2102. Under the above assumptions (a) and (b), the output voltage of the odd-numbered output terminal has the offset voltage A or −A when an output voltage having positive polarity should be outputted from the odd-numbered output terminal, and the output voltage of the odd-numbered output terminal has the offset voltage B or −B when an output voltage having negative polarity should be outputted from the odd-numbered output terminal. The polarity of the offset voltage is selected in accordance with the switch changeover signal of the foregoing operational amplifier.
FIG. 3 shows a concrete example of the structure of the differential amplifier circuit 2115 shown in FIGS. 40 and 41. In FIG. 3, the reference numeral 2301 corresponds to the operational amplifier of N-channel MOS transistor input type shown in FIG. 34, the reference numeral 2302 corresponds to the operational amplifier of P-channel MOS transistor input type shown in FIG. 37. In FIG. 3, the reference numerals 2307 and 2308 respectively correspond to the switches 2107 and 2108 shown in FIGS. 40 and 41. Output terminals 2311 and 2312 of FIG. 3 respectively correspond to the output terminals 2111 and 2112 shown in FIGS. 40 and 41. VBN and VBP shown in FIG. 3 indicate the bias voltage input terminals for providing the operating points of the operational amplifiers, respectively. In FIG. 3, the reference numerals 2313 corresponds to the reference numeral 2113 (the alternation switch changeover signal input REV), the reference numerals 2314 corresponds to the reference numeral 2114 (the switch changeover signal SWP of the operational amplifier shown in FIGS. 34 and 37) shown in FIGS. 40 and 41.
FIG. 42 and Table 1 show the relation among an alternation switch changeover signal REV, a switch changeover signal SWP of the operational amplifier, and the outputs.
In FIG. 42, the reference numeral 2601 indicates an idealistic pixel voltage that is driven by the output voltage outputted from the odd-numbered output terminal. The reference numeral 2602 indicates an actual pixel voltage including an offset voltage. The alternation switch changeover signal REV is inverted for every frame, and the switch changeover signal SWP of the operational amplifier is inverted for every two frames. As a result, the difference between the idealistic pixel voltage and the actual pixel voltage changes for every frame, i.e., successively changes as A, B, −A, and −B in this order. Accordingly, it takes four frames for the difference to return to the original state.
The deviation between the first frame and the third frame and the deviation between the second frame and the fourth frame have a same value and have polarities that are reversed to each other, respectively. When the period (cycle) of the frame is short enough compared to the reaction time of the liquid crystal material, (a) the deviations are canceled between the first and third frames and (b) the deviations are canceled between the second and fourth frames. At the even-numbered output terminals, similarly, the deviations are canceled for every four frames. Table 1 shows the fact.
TABLE 1INPUT SIGNALOUTPUT TERMINALSWPREVODD-NUMBEREDEVEN-NUMBEREDLOWLOWPOSITIVE POLARITYNEGATIVE POLARITYLEVELLEVEL(DEVIATION A)(DEVIATION B)LOWHIGHNEGATIVE POLARITYPOSITIVE POLARITYLEVELLEVEL(DEVIATION B)(DEVIATION A)HIGHLOWPOSITIVE POLARITYNEGATIVE POLARITYLEVELLEVEL(DEVIATION −A)(DEVIATION −B)HIGHHIGHNEGATIVE POLARITYPOSITIVE POLARITYLEVELLEVEL(DEVIATION −B)(DEVIATION −A)
Thus, the unevenness of the deviations that are occurred for every liquid crystal driving output terminal is canceled in each display pixel, thereby ensuring that the display of high quality is carried out without being discerned as the display unevenness by the human eyes.
However, according to the foregoing conventional arts, each offset voltage happens to be generated due to the reasons such as the unevenness of the structural conditions in the differential amplifier (operational amplifier circuit) that constitutes the output circuit section (see FIG. 17) of the source driver. Each offset voltage is mainly generated in the differential section constituting the inputting stage of the differential amplifier. Each offset voltage causes an error with respect to an idealistic driving voltage to be applied to the liquid crystal display device, thereby resulting in that the display image is not appropriately displayed. This results in the display unevenness that causes the lowering of the display quality.
According to the first conventional art, the operational amplifier having an N-channel MOS transistor as its inputting stage and the operational amplifier having a P-channel MOS transistor as its inputting stage are provided so as to output a voltage having positive polarity and a voltage having negative polarity via a single output terminal (i.e., in a full range), respectively. This allows to cancel, in two frames, the deviations A and −A derived from the offset voltage as shown in FIG. 21.
However, since the circuit configuration requires two operational amplifiers for each output terminal, the problem that the scale of the circuit becomes large and its chip size becomes larger arises. In addition, since the number of operational amplifier circuits whose power consumption is relatively large increases, the low power consumption is hard to achieve.
Meanwhile, according to the second conventional art, (a) a voltage having positive polarity is outputted from the operational amplifier in which N-channel MOS transistors are adopted as its inputting stage, (b) a voltage having negative polarity is outputted from the operational amplifier in which P-channel MOS transistors are adopted as its inputting stage, and (c) the voltage having positive polarity and the voltage having negative polarity are switched by the changeover switch so as to output the output voltage in a full range. This allows that the number of the operational amplifiers is reduced by half, thereby realizing the reduction of the circuit scale and the low power consumption.
However, according to the second conventional art as shown in FIG. 20, it is not possible to cancel (a) the deviation A derived from the offset voltage that is generated by the operational amplifier circuit adopting N-channel MOS transistors with (b) the deviation B derived from the offset voltage that is generated by the operational amplifier circuit adopting P-channel MOS transistors, and (c) it is not also possible to cancel the error with respect to the idealistic driving voltage to be applied to the liquid crystal display device. This causes that the display image is not appropriately displayed, i.e., a so-called display unevenness occurs. These deficiencies were main reasons why the display quality is lowered.
According to the third conventional art, (a) a voltage having positive polarity is outputted from the operational amplifier in which N-channel MOS transistors are adopted as its inputting stage, (b) a voltage having negative polarity is outputted from the operational amplifier in which P-channel MOS transistors are adopted as its inputting stage, (c) the voltage having positive polarity and the voltage having negative polarity are switched by the changeover switch so as to output the output voltage in a full range, and (d) the noninverted input signal or inverted input signal is switched and inputted as the input signal to the input terminals (noninverted input terminal or inverted terminal) so as to newly generate another voltage having positive polarity and a further voltage having negative polarity (that are resultants of inversion of the foregoing respective voltages having positive and negative polarities) in accordance with the above changing of the input signals, in addition to the foregoing voltages having positive and negative polarities, thereby resulting in that the deviations A, B, −A, and −B are changed for every frame so as to cancel the deviations in four frames (see FIG. 42 and Table 1). The deviations A and −A are derived from the offset voltage that has been generated in the operational amplifier adopting the N-channel MOS transistors, and the deviations B and −B are derived from the offset voltage that has been generated in the operational amplifier adopting the P-channel MOS transistors. Thus, a so-called display unevenness can be eliminated.